IEEE

Design and Implementation of a Line Array CMOS High-Speed Acquisition System Using FPGA

Abstract: This paper presents the design of a high-speed acquisition system for linear CMOS sensors based on an FPGA. The system utilizes the Hamamatsu S11108 linear CMOS as the image sensor. An FPGA ...
IEEE

FPGA Implementation of High-Speed Accelerators for CNN Architecture Using 3D Systolic Array Architecture

Abstract: Convolution Neural Networks (CNNs) are pivotal in image processing. Prominent CNN models include SqueezeNet, MobileNet, Xception, VGG-16, and AlexNet. These models transform 2D data to 1D, ...